CDR circuits (or systems) are generally used to sample an incoming data signal, extract the clock from the incoming data signal, and retime the sampled data. A phase-locked loop (PLL) based CDR circuit is a conventional type of CDR circuit that utilizes negative feedback. A PLL circuit responds to both the frequency and the phase of a reference signal, automatically raising or lowering the frequency of a voltage-controlled oscillator (VCO) until it is matched to the reference signal in both frequency and phase. In simpler terms, a PLL compares the phases of two signals and produces an error signal which is proportional or otherwise dependent on the difference between the input phases. The error signal is then low-pass filtered by a loop filter and used to drive the VCO which creates an output clock frequency. The output clock frequency is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output clock frequency drifts, the error signal will increase, driving the frequency in the opposite direction so as to reduce the error. Thus the circuit attempts to lock the frequency of the output clock to the frequency at the reference input. The dynamics of the loop are generally determined by the open loop gain and the location of open loop zeroes and poles (predominantly in the loop filter).
Conventional CDR circuits based on a PLL architecture suffer from large jitter of the VCO, coming from both noise generated in the VCO and the noise on the control voltage input to the VCO. A low-gain VCO, desired to reduce this noise, normally compromises the requirement for the total loop gain and the tuning range of the VCO, which is related to the range of data rates that the CDR supports.